The open architecture of the RISC-V instruction set, developed at the University of California, Berkeley in 2010, has become widely used in academia and industry due to its lack of licensing fees and modular structure [1]. According to RISC-V International, the organization has more than 3,000 members from leading technology companies and universities around the world.

However, the widespread adoption of RISC-V in educational and research projects faces a significant challenge: the high complexity and labor intensity of the verification process for developed processor cores. According to semiconductor industry statistics, verification accounts for 50 to 80 % of the total SoC development time, and the cost of undetected errors grows exponentially at each subsequent stage of the product life cycle [2].

The goal of this research is to develop a universal verification environment that lowers the entry threshold for developers into RISC-V core architectural verification by maximizing the automation of the compliance testing process.

Analysis of existing approaches to verification

Modern approaches to processor verification include several methods. Formal verification uses mathematical tools (model checking, theorem proving) to prove the correctness of the system. However, complete formal verification of a real processor core remains unattainable due to the problem of state space explosion.

Simulation verification based on UVM (Universal Verification Methodology) is an industry standard, but it requires deep expertise in SystemVerilog and significant time to create a testbench for each core.

Compliance testing focuses on confirming compliance with the official ISA specification through a set of riscv-arch-test architectural tests approved by RISC-V International. RiscoF (RISC-V Compatibility Framework) automates the process of running architectural tests through a modular architecture: the framework core manages testing, and adapter plugins provide an interface to specific processor implementations.

The analysis revealed the following critical barriers to the implementation of verification:

1. High entry threshold: professional EDA tools cost tens of thousands of dollars. Open-source alternatives require significant effort to set up.
2. Manual environment setup: integrating a new core with RiscoF requires creating a unique plugin and testbench, which can take weeks or months of work.
3. Lack of universal solutions: each team creates its own environment without the possibility of reusing components.
4. Fragmented documentation: information is scattered across various sources without a centralized guide.

Architecture of the proposed solution

The developed verification environment is based on the principles of modularity and configurability. Key components of the system include:

 a universal adapter (plugin) for RiscoF, parameterized via a YAML file;

 a library of SystemVerilog testbench templates for various interfaces;

 an automation system based on Make/Python scripts;

 an HTML report generator with detailed test results.

The design principles are based on configuration through declarative description: the user describes the parameters of the target core (ISA, bus type, paths to RTL) in a YAML file. The system automatically generates the necessary components. The testbench library covers common protocols (AXI4, Wishbone), allowing cores to be connected without writing code from scratch.

The system's algorithm includes the following steps:

1. Parsing the YAML configuration file with core parameters.
2. Automatic generation of the RiscoF plugin and testbench.
3. Compiling riscv-arch-test tests for the target ISA configuration.
4. Running a simulation for each test using Verilator.
5. Extracting signatures and comparing them with reference values.
6. Generating a detailed HTML report with coverage metrics.

Implementation and technical stack

The technical stack for implementation includes:

 Adapter implementation language: Python 3.8+;

 RTL simulator: Verilator (open-source);

 Hardware description languages: SystemVerilog for testbenches;

 Configuration: YAML;

 automation: Make, Bash/Python scripts.

The implementation supports the following ISA configurations: RV32I, RV32IM, RV32IMC (with the possibility of expansion); interfaces: AXI4 (priority for SoC integration); simulators: Verilator, with the possibility of adding commercial ones.

The structure of the configuration file is as follows:

core:

name: «example_core»

isa: «RV32IMC»

bus_interface: «axi4"

paths:

rtl_dir: "./rtl»

top_module: «core_top»

simulation:

simulator: «verilator»

timeout: 10000

clock_period: 10ns

Experimental evaluation

The following quantitative metrics were defined to evaluate the effectiveness of the developed solution:

1. Configuration time: the time from receiving the RTL code to the first successful run of the compliance test. Target value: no more than 8 hours.
2. Degree of automation: the proportion of stages performed without manual intervention. Target value: ≥ 40 %.
3. Coverage completeness: the proportion of successfully run official RiscoF tests. Target value: 100 % (with correct core implementation).

Testing is performed on a set of open-source RISC-V cores of varying complexity: PicoRV32 (basic RV32I), SCR1 (RV32IMC), Rocket (RV64GC). For each core, the time spent on the configuration stages, the number of manual interventions required, and the final coverage of the test set are recorded.

Expected results:

The application of the developed verification environment should ensure:

1. Lowering the entry threshold: students and researchers without deep expertise in verification will be able to check the compliance of their cores.
2. Reducing configuration time: from weeks of manual work to a few hours of automatic configuration.
3. Standardization of the process: a unified approach to verifying different cores based on the official RiscoF framework.
4. Improved quality: objective verification of compliance with the RISC-V International specification increases the reliability of the processors being developed.

The developed universal verification environment for automated testing of RISC-V processor cores solves the critical problem of high entry barriers to architectural verification. The modular architecture based on the official RiscoF framework, a parameterizable adapter, and a library of template components enable rapid integration of various cores with minimal time expenditure.

The proposed solution is particularly relevant for educational institutions, research laboratories, and the open-source community, where limited resources do not allow the use of expensive commercial verification tools. Future research directions include expanding support for additional ISA extensions (F, D, V), integration with coverage-driven verification methodologies, and development of a template library for specialized applications.

References:

1. The RISC-V Instruction Set Manual, Volume I: Unprivileged ISA. RISC-V International, 2023.
2. Aouadja R. SoC Regression Strategy Development. Master's Thesis. University of Oulu, Degree Programme in Computer Science and Engineering, 2023. 52 p.